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Projecte llegit

Títol: Diseño e implementación, utilizando el Versal ACAP SoC, de un sistema de formación de haces digitales en el dominio del tiempo de múltiples haces para 5G

Estudiants que han llegit aquest projecte:

Director/a: BERENGUER I SAU, JORDI

Departament: TSC

Títol: Diseño e implementación, utilizando el Versal ACAP SoC, de un sistema de formación de haces digitales en el dominio del tiempo de múltiples haces para 5G

Data inici oferta: 18-09-2025     Data finalització oferta: 18-04-2026


Estudis d'assignació del projecte:
    GR ENG SIS TELECOMUN
Tipus: Individual
 
Lloc de realització: Fora UPC    
 
        Supervisor/a extern: Alessandro Modigliana
        Institució/Empresa: SATELIOT
        Titulació del Director/a: Telecommunications engineering master
 
Paraules clau:
5G, Array, Antennas, Beamforming, Versal, Procesadores DSP
 
Descripció del contingut i pla d'activitats:
In this project it will first be studied the theory and then characterised the behaviour and performance of a multi-beam time-domain digital beamformer for an array antenna using Matlab. Then it will be explored and compared with the various algorithm implementations of a time-domain digital beamforming algorithm, and the selected one will be implemented in Matlab. As a final point the selected algorithm will be adapted to a Digital Signal Processor, adapting the algorithm to take advantage of vector/parallel processing in order to have a real-time and low power implementation suitable for a deployment in a commercial environment.

The project will be structured in the following parts:

1. Study of the fundamental beam forming theory
2. Characterisation of beam patterns for different beam steering, for single and multiple beams, and comparison with provided CST simulations
3. Characterisation of the beam-to-beam interference in a multi-beam scenario
4. Implement techniques for beam-to-beam interference reduction
5. Compare different digital beam forming algorithm implementations and implements the selected one in Matlab using vector instructions and external 5G test vectors
6. Rewrite the digital beam forming algorithm in C++ and update the algorithm to take advantage of vector instructions supported by the AI Engine nodes.
7. Deploy the software on a Versal AI Edge SoC and compare the antenna patterns against the Matlab version using the same 5G test vectors (in a single beam and multi beam scenario)
8. Profiling and further code optimization on Versal AI Edge SoC
9. Emulate Real-Time input (Az, El) and perform beamforming update at different periodicity for comparison.
 
Overview (resum en anglès):
This Bachelor's Thesis addresses the design and implementation of a multi-beam digital beamforming algorithm for 5G satellite communications, developed in collaboration with Sateliot.

Due to the growing demand for massive connectivity from low Earth orbit constellations, information addressing architectures are required that can meet the latency and performance requirements that classic sequential processors, such as general-purpose CPUs or FPGAs, cannot natively support.

This work proposes a parallel implementation of the beamforming algorithm that leverages the vectorized processing engines of a heterogeneous system-on-a-chip, the Versal ACAP adaptive computing acceleration platform. The development begins with an ideal mathematical and geometric model of beamforming in the time domain and culminates in the design of a beamforming algorithm for DSP processors, enabling them to perform the operations on the satellite.

This methodology was applied to two successive generations of Versal hardware: an initial prototyping platform used to validate the vectorized and experimental approach, and a production platform representing the final target architecture.

The solution allows for the dynamic shaping of simultaneous beams across 64 antennas, maintaining processing within the real-time budgets required by the 5G standards the company is addressing. Functional validation confirms adequate signal fidelity compared to the theoretical reference model defined in Matlab.

The resulting design aims to meet the requirements for the satellite's production stage, complying with the required standards without the need for hardware reconfiguration. Validation on real uplink hardware and comparison with additional simulations of the complete antenna pattern remain as future lines of work.

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